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march 2002 copyright ? alliance semiconductor. all rights reserved. as7c4096 as7c34096 5v/3.3v 512k 8 cmos sram ? 5/23/02; v.1.8 alliance semiconductor p. 1 of 10 features ? as7c4096 (5v version) as7c34096 (3.3v version) industrial and commercial temperature organization: 524,288 words 8 bits center power and ground pins high speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time low power consumption: active - 1375 mw (as7c4096) / max @ 12 ns - 468 mw (as7c34096) / max @ 12 ns low power consumption: standby - 110 mw (as7c4096) / max cmos - 72 mw (as7c34096) / max cmos equal access and cycle times easy memory expansion with ce , oe inputs ttl-compatible, three-state i/o jedec standard packages - 400 mil 36-pin soj - 44-pin tsop 2 esd protection 2000 volts latch-up current 200 ma logic block diagram 524,288 8 array (4,194,304) sense amp input buffer i/o8 i/o1 oe ce we column decoder row decoder control circuit a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd a8 a10 a11 a12 a13 a14 a15 a16 a17 a18 a9 pin arrangement s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 a15 oe i/o8 i/o7 gnd v cc i/o6 i/o5 a14 a13 a12 a11 a10 nc a0 a1 a2 a3 a4 ce i/o1 i/o2 v cc gnd i/o3 i/o4 we a5 a6 a7 17 18 a8 a9 36 35 34 33 nc a18 a17 a16 gnd v cc i/o6 i/o5 nc a14 a13 a12 a11 a10 a4 ce i/o1 i/o2 v cc gnd i/o3 i/o4 we a5 a6 a7 a8 a9 i/o8 i/o7 a1 a2 a3 a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a16 a15 a17 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2 3 4 1 nc nc nc nc nc nc nc nc nc oe a18 36-pin soj (400 mil) 44-pin tsop 2 48-pin bga package 1 2 3 4 5 6 a a 0 a 1 nc a 3 a 6 a 8 b i/o 5 a 2 we a 4 a 7 i/o 1 c i/o 6 nc nc a 5 nc i/o 2 d v ss nc nc nc nc v cc e v cc nc nc nc nc v ss f i/o 7 nc a 18 a 17 nc i/o 3 g i/o 8 oe ce a 16 a 15 i/o 4 h a 9 a 10 a 11 a 12 a 13 a 14 selection guide ?10 ?12 ?15 ?20 unit maximum address access time 10 12 15 20 ns maximum outputenable access time 5 6 7 9 ns maximum operating current as7c4096 ? 250 220 180 ma as7c34096 160 130 110 100 ma maximum cmos standby current as7c4096 ? 20 20 20 ma as7c34096 20 20 20 20 ma
? as7c4096 as7c34096 5/23/02; v.1.8 alliance semiconductor p. 2 of 10 functional description the as7c4096 and as7c34096 are high-performance cmos 4,194 ,304-bit static random access memory (sram) devices organized as 524,288 words 8 bits. they are designed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with output enable access times (t oe ) of 5/6/7/8 ns are ideal for high-performance applications. the chip enable input ce permits easy memory expansion with multiple-bank memory systems. when ce is high the device enters standby mode. the as7c4096 is guaranteed not to exceed 110 mw power consumption in cmos standby mode. a write cycle is accomplished by asserting write enable (we ) and chip enable (ce ). data on the input pins i/o1?i/o8 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and chip enable (ce ), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input address. wh en either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. all chip inputs and outputs are ttl-compatible, and operation is from a single supply voltage. both devices are available in th e industry standard 400-mil 36-pin soj and 44-pin tsop 2 packages. note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional oper- ation of the device at these or any other conditions outside th ose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. key: x = don?t care, l = low, h = high absolute maximum ratings parameter device symbol min max unit vo l t ag e o n v cc relative to gnd as7c4096 v t1 ?1 +7.0 v as7c34096 v t1 ?0.5 +5.0 v voltage on any pin relative to gnd v t2 ?0.5 v cc +0.5 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 c temperature with v cc applied t bias ?55 +125 c dc current unto output (low) i out ?20ma truth table ce we oe data mode h x x high z standby (i sb , i sb1 ) l h h high z output disable (i cc ) lhl d out read (i cc ) llx d in write (i cc )
? as7c4096 as7c34096 5/23/02; v.1.8 alliance semiconductor p. 3 of 10 recommended operating condition parameter device symbol min nominal max unit supply voltage as7c4096 v cc (12/15/20) 4.5 5.0 5.5 v as7c34096 v cc (10) 3.15 3.30 3.6 v as7c34096 v cc (12/15/20) 3.0 3.3 3.6 v input voltage as7c4096 v ih 2.2 ? v cc + 0.5 v as7c34096 v ih 2.0 ? v cc + 0.5 v v il ?0.5 1
?0.8v ambient operating temperature commercial t a 0? 70 c industrial t a ?40 ? 85 c dc operating characteristics (over the operating range ) parameter symbol test conditions device ?10 ?12 ?15 ?20 unit min max min max min max min max input leakage current |i li |v cc = max, v in = gnd to v cc ?1?1?1?1 a output leakage current |i lo | v cc = max, ce = v ih v out = gnd to v cc ?1?1?1?1 a operating power supply current i cc v cc = max, ce < v il f = f max , i out = 0ma as7c4096 ? ? ? 250 ? 220 ? 180 ma as7c34096 ? 160 ? 130 ? 110 ? 100 standby power supply current i sb v cc = max, ce = v ih f = f max , i out = 0ma as7c4096 ? ? ? 60 ? 60 ? 60 ma as7c34096 ? 60 ? 60 ? 60 ? 60 i sb1 v cc = max, ce v cc ? 0.2v, v in 0.2v or v in v cc ? 0.2v, f = 0 as7c4096 ? ? ? 20 ? 20 ? 20 ma as7c34096 ? 20 ? 20 ? 20 ? 20 output voltage v ol i ol = 8 ma, v cc = min ?0.4?0.4?0.4?0.4v v oh i oh = ?4 ma, v cc = min 2.4 ? 2.4 ? 2.4 ? 2.4 ? v c apacitance (f = 1mhz, t a = 25 c, v cc = nominal) parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
? as7c4096 as7c34096 5/23/02; v.1.8 alliance semiconductor p. 4 of 10 key to switching waveforms read waveform 1 (address controlled) read waveform 2 (ce , oe controlled) read cycle (over the operating range) parameter symbol ?10 ?12 ?15 ?20 unit notes min max min max min max min max read cycle time t rc 10 ? 12 ? 15 ? 20 ? ns address access time t aa ? 10 ? 12 ? 15 ? 20 ns 3 chip enable (ce ) access time t ace ? 10 ? 12 ? 15 ? 20 ns 3 output enable (oe ) access time t oe ?5?6?7?8ns output hold from address change t oh 3?3?3?3?ns5 ce low to output in low z t clz 3?3?0?0?ns4, 5 ce high to output in high z t chz ?5?6?7?9ns4, 5 oe low to output in low z t olz 0?0?0?0?ns4, 5 oe high to output in high z t ohz ?5?6?7?9ns4, 5 power up time t pu 0?0?0?0?ns4, 5 power down time t pd ? 10 ? 12 ? 15 ? 20 ns 4, 5 undefined/don?t care falling input rising input address d out data valid t oh t aa t rc current supply oe d out t oe t olz t ace t chz t clz t pu t pd i cc i sb 50% 50% t ohz data valid t rc1 ce
? as7c4096 as7c34096 5/23/02; v.1.8 alliance semiconductor p. 5 of 10 write waveform 1 (we controlled) write waveform 2 (ce controlled) write cycle (over the operating range) parameter symbol ?10 ?12 ?15 ?20 unit notes min max min max min max min max write cycle time t wc 10?12?15?20?ns chip enable (ce ) to write end t cw 7?8?10?12?ns address setup to write end t aw 7?8?10?12?ns address setup time t as 0?0?0?0?ns write pulse width (oe = high) t wp1 7?8?10?12?ns write pulse width (oe = low t wp2 10?12?15?20?ns address hold from end of write t ah 0?0?0?0?ns write recovery time t wr 0?0?0?0?ns data valid to write end t dw 5?6?7?9?ns data hold time t dh 0?0?0?0?ns4, 5 write enable to output in high z t wz 05060709ns4, 5 output active from write end t ow 3?3?3?3?ns4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t wr t aw address ce we d out t cw t wp t dw t dh t ah t wz t wc t as data valid d in t wr
? as7c4096 as7c34096 5/23/02; v.1.8 alliance semiconductor p. 6 of 10 ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions . 4t clz and t chz are specified with c l = 5pf as in figure c. transition is measured 500 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7ce and oe are low for read cycle. 8 address valid prior to or coincident with ce transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce or we must be high during address transitions. either ce or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the la st valid address to the fi rst transitioning address. 12 not applicable. 13 c = 30pf, except at high z and low z parameters, where c = 5pf. 350 ? c(14) 320 ? d out gnd +3.3v figure c: 3.3v output load - output load: see figure b or figure c. - input pulse level: gnd to 3.0v. see figures a, b, and c. - input rise and fall times: 2 ns. see figure a. - input and output timing reference levels: 1.5v. 168 ? thevenin equivalent: d out +1.728v 255 ? c(14) 480 ? d out gnd +5v figure b: 5v output load 10% 90% 10% 90% gnd +3.0v figure a: input pulse 2 ns
? as7c4096 as7c34096 5/23/02; v.1.8 alliance semiconductor p. 7 of 10 typical dc and ac characteristics
supply voltage (v) min max nominal 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb ambient temperature ( c) ?55 80 125 35 ?10 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb vs. ambient temperature t a vs. supply voltage v cc i cc i sb i cc i sb ambient temperature ( c) ?55 80 125 35 ?10 0.2 1 0.04 5 25 625 normalized i sb1 (log scale) normalized supply current i sb1 vs. ambient temperature t a v cc = v cc (nominal) supply voltage (v) min max nominal 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa ambient temperature ( c) ?55 80 125 35 ?10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa cycle frequency (mhz) 075 100 50 25 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current i cc vs. ambient temperature t a vs. cycle frequency 1/t rc , 1/t wc vs. supply voltage v cc v cc = v cc (nominal) v cc = v cc (nominal) t a = 25 c t a = 25 c output voltage (v) v cc 0 20 60 80 40 100 120 140 output source current (ma) output source current i oh output voltage (v) v cc output sink current (ma) output sink current i ol vs. output voltage v ol vs. output voltage v oh 0 20 60 80 40 100 120 140 capacitance (pf) 0 750 1000 500 250 0 5 15 20 10 25 30 35 change in t aa (ns) typical access time change ? t aa vs. output capacitive loading 00 v cc = v cc (nominal) v cc = v cc (nominal) v cc = v cc (nominal) t a = 25 c t a = 25 c
? as7c4096 as7c34096 5/23/02; v.1.8 alliance semiconductor p. 8 of 10 package dimensions 44-pin tsop 2 min(mm) max(mm) a 1.2 a 1 0.05 0.15 a 2 0.95 1.05 b 0.30 0.45 c 0.15 (typical) d 18.28 18.54 e 1 10.03 10.16 e 11.56 11.96 e 0.80 (typical) l 0.40 0.60 36-pin soj 400 min(mils) max(mils) a .128 0.148 a 1 0.027 ? a 2 0.102 nom b 0.015 0.020 b 1 0.026 0.032 c 0.007 0.013 d .920 .930 e 0.045 0.055 e 0.400 nom e 0.435 0.445 d e 1234567891011121314 4443424140393837363534333231 1516 30 29 17181920 28 2726 25 c l a 1 a 2 e 44-pin tsop 2 0?5 21 24 23 e 1 a b seating plane 22 d pin 1 e e 1 e 2 a2 c a1 b 1 b a e !"#
? as7c4096 as7c34096 5/23/02; v.1.8 alliance semiconductor p. 9 of 10 48-ball fbga side view detail view e e2 e1 d die a e e2 0.3/typ y die ball #a1 to p vi ew ball #a1 index bottom view 1 2 3 4 5 6 a c d e f g h b a a b1 c1 sram die c elastomer b 48-ball fbga minimum ty p i c a l maximum a ?0.75? b 6.90 7.00 7.10 b1 ?3.75? c 10.90 11.00 11.10 c1 ?5.25? d 0.30 0.35 0.40 e ??1.20 e1 ?0.68? e2 0.22 0.25 0.27 y ??0.08 notes 1. bump counts: 48 (8 row 6 column). 2. pitch: (x,y) = 0.75 mm 0.75 mm (typ). 3. units: millimeters. 4. all tolerance are 0.050 unless otherwise specified. 5. typ: typical. 6. y is coplanarity: 0.08 (max).
? copyright alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. al l other brand and product names may be the trade- marks of their respective companies. alliance reserves the right to make changes to this documen t and its products at any time without notice. allia nce assumes no responsibility for any erro rs that may appear in this document. the data contained herein represents alliance?s best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, w ithout notice. if the product described herein is under development, significant changes to these specifications are po ssible. the information in this product data shee t is intended t o be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or custom er. alliance does not assume any responsibility or liability ar ising out of the application or use of any produc t described herein, and disclaims any express or implied warranties related to the sale a nd/or use of alliance products including liab ility or warranties rela ted to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance?s terms and conditions of sale (w hich are available from alliance) . all sales of alliance product s are made exclusively according to alliance? s terms and conditions of sale. the purchase of products from alliance does not convey a licen se under any patent rights, copyrights, ma sk works rights, trademarks, or any oth er intellectual property rights of alliance or th ird parties. alliance does not authorize its products for use as critical components in life-suppor ting systems where a malfunction or failure may reasonably be expected to result i n significant injury to the user, and the inclus ion of alliance products in such life-supporting sys- tems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising fro m such use. ? as7c4096 as7c34096 5/23/02; v.1.8 alliance semiconductor p. 10 of 10 ordering codes package ve r s i o n 10 ns 12 ns 15 ns 20 ns soj 5v commercial na as7c4096-12jc as7c4096-15jc as7c4096-20jc 5v industrial na as7c4096-12ji as7c4096-15ji as7c4096-20ji 3.3v commercial as7c34096-10jc as7c 34096-12jc as7c34096-15jc as7c34096-20jc 3.3v industrial na as7c34096-12ji as7c34096-15ji as7c34096-20ji tsop 2 5v commercial na as7c4096-12tc as7c4096-15tc as7c4096-20tc 5v industrial na as7c4096-12ti as7c4096-15ti as7c4096-20ti 3.3v commercial as7c34096-10tc as7c 34096-12tc as7c34096-15tc as7c34096-20tc 3.3v industrial na as7c34096-12ti as7c34096-15ti as7c34096-20ti bga 5v commercial na as7c4096-12bc as7c4096-15bc as7c4096-20bc 5v industrial na as7c4096-12bi as7c4096-15bi as7c4096-20bi 3.3v commercial as7c34096-10bc as7c34096-12bc as7c34096-15bc as7c34096-20bc 3.3v industrial na as7c34096-12bi as7c34096-15bi AS7C34096-20BI part numbering system as7c x 4096 ?xx j, t, or b x sram prefix vo l t ag e : blank: 5v cmos 3: 3.3v cmos device number access time packages: j: soj 400 mil t: tsop 2 b: 48-ball fbga 7x11 mm temperature ranges: c: commercial, 0c to 70c i: industrial, ?40c to 85c

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